1. Field of the Invention
The present invention relates to routing data packets in a computer network. In particular, the present invention relates to routing data packets in a computer network in which equal cost multi-path (ECMP) load sharing is available.
2. Discussion of the Related Art
In a router, a data packet is directed from an input port to an output port based on the data specified in the header of the data packet. Typically, a content addressable memory (CAM) quickly maps the IP header information or layer 3 header of the data packet to a memory location of a parameter random access memory (PRAM) which stores information that indicates the route over which the data packet should be forwarded, and the parameter values relevant to the route. In one prior art router, the data stored in the PRAM includes a forwarding identifier (FID), types of service (TOS), priority, number of copies (e.g., a multicast address) and other information. The circuit including the CAM and the PRAM is sometimes referred to as a “packet classifier.” The packet classifier encodes the FID and other data into an internal header for the data packet which is used by the router to direct the data packet at line speed to an output port, where the data packet is forwarded to the next switch on a path to its destination.
In that prior art router, the CAM entries are mapped one-to-one to the PRAM entries. That is, only one FID can result from the CAM look-up based on the header of the data packet. In an Internet Protocol (IP) network, a data packet may be routed through any of a number of paths through multiple switches to its destination. ECMP load sharing is one method known to those skilled in the art by which multiple-path routing of IP data traffic can be accomplished. One method to support ECMP is to resolve the level 3 (IP layer) and level 4 (“transport control protocol” or TCP layer) headers of a data packet into any one of a number of FIDs, where each FID represents a different output port of the router that is connected to a switch on a different one of the possible paths for the data packet. However, because the CAM entries are mapped one-to-one with the PRAM entries, the prior art router does not provide efficient hardware support for ECMP load sharing.
“JetCore™ Based Chassis System: An Architecture Brief on NetIron, BigIron and FastIron Systems” and “Next Generation Terabit System Architecture: The High Performance Revolution for 10 Gigabit Networks” are white papers available from Foundry Networks, Inc. that disclose designs for high performance routers in the prior art. These white papers are hereby incorporated by reference in their entireties to provide background information.